As process technologies scale (or shrink), transistor leakage increases for the same power supply level. Increase in leakage increases power consumption. As market converges to lower power consumption devices, there is a need to reduce power consumption including reducing leakage power of a device.
Conventional memory cells, for example, status random access memory (SRAM) cells have a p-type sleep transistor between a memory cell and a power grid, or a n-type sleep transistor between ground and the virtual ground of the memory cell. When a memory array (having memory cells) is not being accessed (e.g., in idle mode), the sleep transistor is enabled i.e., is turned ON. The p-type sleep transistor is usually high impedance transistor which causes the supply to the memory cell to reduce resulting in leakage reduction in the memory cell. Due to possible data retention failures at the minimum operating voltage (also called Vmin), memories are optimized to have a particular size (W/L) for the sleep transistor.
However, operating voltage of devices is becoming wider (e.g., 650 mV to Vmax), where Vmax is maximum operating voltage. Vmax is dependent on process technology node. In one example, Vmax is around 1V to 1.1V. Existing sleep schemes are inefficient at higher power supply levels because the sleep transistor size is designed for a particular operating voltage. At higher operating voltages, leakage power increases.